Circuit to minimize local clock frequency disturbances when phase locking to a reference clock circuit
US4503400A · kind A · utility
4Cited by
3References
30Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 23, 1983 |
| Grant date | Mar 5, 1985 |
| Priority date | — |
| Expiry date | Jun 23, 2003 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/10
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A frequency disturbance minimization circuit for use in a phase locked loop circuit. A pulse generator eliminates random phase shift, which occurs after a reference clock outage, by synchronizing counted down derivatives of the local and reference clock circuits. A window circuit provides a signal representative of the difference in phase between these local and reference clock circuits. A counter accumulates these phase difference window signals for periodic interrogation by a microprocessor which causes a voltage controlled oscillator to adjust its frequency in the direction necessary to eliminate this phase difference.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.