Patent · US Expired

Digital frequency/phase locked loop

US4504799A · kind A · utility

26Cited by
6References
35Claims
0Family size

Assignee

Inventors

Key dates

Filing dateJul 10, 1981
Grant dateMar 12, 1985
Priority date
Expiry dateJul 10, 2001

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH03L7/0992
  • WIPO fieldBasic communication processes
  • WIPO sectorElectrical engineering

Abstract

A frequency/phase locked loop for providing signals which are frequency and phase locked to signals at a reference frequency from a reference oscillator which is determinative of the frequency stability includes a frequency-controlled generator of a lower frequency stability. The frequency controlled generator is responsive to control signals for switching between first and second frequencies which are substantially higher than the reference frequency. The second frequency is approximately one to ten percent higher than the first frequency. The frequency divider coupled to the frequency generator provides an output signal at the same frequency as the reference oscillator. A digital phase comparator compares the outputs of the frequency divider with the reference signals. A digital integrating stage coupled to the comparator provides the control signals such that during a first portion of a period of the reference signals the first frequency is selected and during a second portion of the period the second frequency is selected.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.