Process for positioning an interconnection line on an electrical contact hole of an integrated circuit
US4505030A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Apr 12, 1983 |
| Grant date | Mar 19, 1985 |
| Priority date | — |
| Expiry date | Apr 12, 2003 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Process for the positioning of an interconnection line on an electrical contact hole of an integrated circuit, wherein, when the electrical contact hole has been produced, the following stages are performed: PA1 deposition of a conductive layer in which the interconnection line is to be formed on the complete integrated circuit; PA1 deposition on the conductive layer of an insulating layer blanking the relief thereof and having a planar surface, PA1 etching the insulating layer, so that insulating material is only left at the location of the electrical contact hole, PA1 deposition of a resin layer on the integrated circuit, so as to mask the interconnection line to be produced, PA1 etching of that part of the conductive layer which is free from resin and the residual insulating layer, and PA1 elimination of the remaining insulating layer and the resin layer. The positioning process is particularly used in processes for producing MOS integrated circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.