High speed logic flip-flop latching arrangements including input and feedback pairs of transmission gates
US4506167A · kind A · utility
19Cited by
9References
25Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 26, 1982 |
| Grant date | Mar 19, 1985 |
| Priority date | — |
| Expiry date | May 26, 2002 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/356156
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A high speed logic latching circuit consists of a pair of inverters and feedback switches used to latch the inverters. A pair of input switching means allows data to enter the latch when the latch is disabled. This configuration allows for high speed, reduced substrate area and true complementary outputs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.