Systematic memory error detection and correction apparatus and method
US4506362A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jul 26, 1982 |
| Grant date | Mar 19, 1985 |
| Priority date | — |
| Expiry date | Jul 26, 2002 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/2205
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A systematic data memory error detection and correction apparatus periodically reads data from each addressable memory location, determines the presence or absence of an error in the addressed data memory location and, if an error is detected, corrects the error and writes the corrected data back into the addressed memory location. The apparatus may include circuitry for logging those areas of the data memory where errors have been detected, such logging showing either the address location where an error is detected or alternatively indicating the repetitiveness of an error at any particular addressed memory location. Such data logging facilitates determination of hardware or "hard" type errors as distinguished from non-hardware or "soft" type errors. The latter type errors are typically found in dynamic random access memories (dynamic RAM's) which occasionally and randomly have errors due to bombardment of cosmic energy and alpha particles, the latter typically due to minute radioactive elements in silicon materials used in the fabrication of such memories. When the present apparatus is used in conjunction with dynamic RAM's, the error detection and correction is typically perform…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.