Bidirectional data byte aligner
US4507731A · kind A · utility
41Cited by
8References
57Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Nov 1, 1982 |
| Grant date | Mar 26, 1985 |
| Priority date | — |
| Expiry date | Nov 1, 2002 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A byte-addressable memory system having an array of transceivers with control logic which enables memory to be addressable on individual byte boundaries rather than on two byte (word) or four byte (longword) boundaries. The memory system has two independent even-address and odd-address segments allowing parallel access to two longwords (eight bytes or one quadword) simultaneously. Logic determines which of the eight bytes should be placed on a four byte bus and the sequential order of the bytes on the bus. The entire operation takes place in one memory cycles time period and can start at any byte address.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.