Procedure for shared-time processing of digital signals and application to a multiplexed self-adapting echo canceler
US4507747A · kind A · utility
8Cited by
1References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 14, 1983 |
| Grant date | Mar 26, 1985 |
| Priority date | — |
| Expiry date | Jan 14, 2003 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B3/23
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A self-adapting digital filter having one or more processing modules each possessing a delayed discrete value memory, a coefficient memory, two multipliers-accumulators, a variable-amplitude shift register and a summing circuit with the delayed discrete value memories being addressed in a manner producing fictive shifting of their contents.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.