Digital span frame detection circuit
US4507780A · kind A · utility
6Cited by
3References
11Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 22, 1983 |
| Grant date | Mar 26, 1985 |
| Priority date | — |
| Expiry date | Jun 22, 2003 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04Q11/06
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
In a telecommunications switching system, which has a switching network connected to a number of asynchronous digital spans, a digital span frame detection circuit continuously monitors the framing of each of the digital spans. The digital span frame detection circuit checks for both proper framing and super framing, TS bits and FS bits. An ordered examination of each of the number of digital spans will occur. Any digital span which lacks proper framing or super framing will be marked for subsequent processing. These markings will be scanned and submitted for reframing in an ordered fashion.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.