Re-programmable PLA
US4508977A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 11, 1983 |
| Grant date | Apr 2, 1985 |
| Priority date | — |
| Expiry date | Jan 11, 2003 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17712
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
This disclosure relates to a programmable logic array having an AND array disposed for receiving n input signals, an OR array providing k output signals on k output lines and m term lines coupling the AND and OR arrays together. New and improved AND and OR arrays are disclosed wherein the AND array includes n X m cells and each cell has first and second transistor means coupled in series between one of the term lines and a reference potential. Each cell includes a storage element that has an output terminal coupled to the control element of the first transistor means and one of the n input terminals is coupled to the control element of the second transistor means. The OR array includes m X k cells wherein each cell has third and fourth transistor means coupled in series between one of said output lines and a reference potential. Each of the OR array cells also includes a storage element having an output terminal coupled to the control element of the third transistor and one of the m term lines is coupled to the control element of the fourth transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.