Data processing system auto address development logic for multiword fetch
US4511960A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jan 15, 1982 |
| Grant date | Apr 16, 1985 |
| Priority date | — |
| Expiry date | Jan 15, 2002 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/349
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An auto address development logic that, when provided a starting address, is used to develop consecutive addresses as multiple words of information are presented, one word at a time, during multiple consecutive information transfer cycles. The logic retains for use a current address while simultaneously developing the next address so that the next address will be immediately available as the current address at the beginning of the next information transfer cycle. The auto address development logic is used in a system analyzer connected to a data processing system having a common bus over which the CPU, during a first bus cycle, provides a starting address and requests that the memory fetch multiple words of information which are transferred to the CPU, during multiple subsequent responding bus cycles.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.