Semiconductor device fabrication process
US4512076A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 20, 1982 |
| Grant date | Apr 23, 1985 |
| Priority date | — |
| Expiry date | Dec 20, 2002 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/28525
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device fabrication process is provided wherein a first window is formed in a first silicon dioxide layer which is disposed over the surface of a silicon layer to expose a first portion of the silicon layer. A doped region is formed in the first portion of a silicon layer exposed by the first window. A second layer of silicon dioxide is deposited over the surface of the first, previously formed, silicon dioxide layer and over the first portion of the silicon layer exposed by the first window. A second window is formed through the first and second silicon dioxide layers to expose a second, different portion of the surface of the silicon layer. A layer of silicon nitride is disposed over the second layer of silicon dioxide and through the second formed window onto the portion of the silicon layer exposed by such second formed window. The surface of the structure is then masked with windows being formed in such mask over the first and second previously exposed portions of the silicon layer. An etchant is brought into contact with portions of the silicon nitride layer exposed by the windows formed in the mask to selectively remove the portions of the silicon nitride laye…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.