Information processing system
US4513369A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Feb 17, 1982 |
| Grant date | Apr 23, 1985 |
| Priority date | — |
| Expiry date | Feb 17, 2002 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/1081
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An information processing system using a virtual addressing for paging, including a main memory, a memory controller, a central processing unit for processing information and accessing the memory controller with a virtual address, an input/output controller for interfacing input/output devices with the memory controller and the central processing unit, a common bus for interconnecting the memory controller, the central processing unit and the input/output controller with each other. The memory controller includes a translator for translating the virtual address into a real address, whereby the virtual address is available for addressing the main memory after being translated into the real address.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.