Patent · US Expired

Technique of producing tapered features in integrated circuits

US4514252A · kind A · utility

4Cited by
2References
5Claims
0Family size

Assignee

Inventor

Key dates

Filing dateNov 18, 1982
Grant dateApr 30, 1985
Priority date—
Expiry dateNov 18, 2002

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH01L21/31116
  • WIPO fieldSemiconductors
  • WIPO sectorElectrical engineering

Abstract

A technique is presented for producing tapered walls. In accordance with the disclosed technique, a mask is generated on a workpiece and the workpiece is etched through the mask to replicate the mask pattern into the mask. These steps result in walls at the boundaries of the replicated mask features. In many such processes, these walls are either substantially vertical or have an overhanging portion of the walls. In order to taper the walls, the upper corners of the walls are cut away to remove the overhang or to cut the corner back an additional amount to produce a controlled amount of taper.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.