ECL To TTL output stage
US4514651A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 16, 1982 |
| Grant date | Apr 30, 1985 |
| Priority date | — |
| Expiry date | Dec 16, 2002 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/01806
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In a circuit for converting signals having ECL logic levels to a signal having TTL logic levels, the level shift is accomplished using the base-emitter drops of the transistors employed to avoid the speed degradation that accompanies the use of resistors as level shifters. First and second complementary input ECL signals are applied to first and second transistors respectively. The first input signal results in rendering a drive transistor conductive which turns the source transistor means in a push-pull output stage off and the sink transistor in the output stage on. When the second input signal goes high, current is diverted so as to render the drive transistor nonconductive. Additional circuit means are provided for preventing the sink transistor from saturating and for preventing the input of the source transistor means from falling below a predetermined level. Circuit means are also provided for turning the source transistor means off quickly so as to improve the overall speed performance of the circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.