Methods for partitioning mainframe instruction sets to implement microprocessor based emulation thereof
US4514803A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 26, 1982 |
| Grant date | Apr 30, 1985 |
| Priority date | — |
| Expiry date | Apr 26, 2002 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3879
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods of applying LSI and microprocessors to the design of microprocessor-based LSI implementation of mainframe processors are described. A mainframe instruction set is partitioned into two or more subsets, each of which can be implemented by a microprocessor having special on-chip microcode or by a standard off-the-shelf microprocessor running programs written for that purpose. Alternatively, one or more of the subsets can be implemented by a single microprocessor. In addition, a subset of the partitioned instruction set can be implemented by emulating software, by off-chip vertical or horizontal microcode, or by primitives. But, however partitioning is implemented, the end result thereof is to keep the critical flow paths, associated with the most frequently used instruction subset, as short as possible by constraining them to a single chip. The application of this method requires partitioning that makes each identified high performance subset executable on one microprocessor in the current state of technology, a way to quickly pass control back and forth between all of the microprocessors, a suitable way to pass data back and forth between all of the microprocessors, and a tec…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.