Method for manufacturing an electrical interconnection by selective tungsten deposition
US4517225A · kind A · utility
42Cited by
2References
24Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | May 2, 1983 |
| Grant date | May 14, 1985 |
| Priority date | — |
| Expiry date | May 2, 2003 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A structure for an electrical interconnection suitable for a semiconductor integrated circuit is made by a process utilizing selective tungsten deposition at low pressure to form an intermediate conductive layer without significantly ablating nearby insulating material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.