Fault scoring and selection circuit and method for redundant system
US4517639A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 13, 1982 |
| Grant date | May 14, 1985 |
| Priority date | — |
| Expiry date | May 13, 2002 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1675
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a triplex redundant digital control system, one of three computer units is selected for controlling a digital flight control system by using fault scoring and selection logic circuitry that responds to discrete signals produced by the computer units that represent both self-test and cross-test information on the health of the three available units. The self-test and cross-test discrete information signals are received and processed by the selection logic circuit in accordance with a fault-scoring scheme in which the self-test scores are accorded different and, in particular, greater weight than the cross-test scores and a computer unit exhibiting the lowest combined self- and cross-test fault score is selected as the computer in control. The circuitry also includes memory devices for storing the fault scores associated with previous fault conditions so that a previously unfailed computer unit is selected over a previously failed but currently healthy computer. The memory devices are cleared whenever all three computer modules have scored a fault condition of equal weight such that transient failures do not cause permanent disablement of a computer unit, rather the temporarily fa…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.