Method and arrangement for an operational check of a programmable logic array

US4517672A · kind A · utility

Assignee

• Siemens Aktiengesellschaft · DE

Inventors

• Hans-Joerg Pfleiderer
• Gerhard Grassl · Grafing, DE

Key dates

• Filing date: Jul 23, 1982
• Grant date: May 14, 1985
• Expiry date: Jul 23, 2002

Classification

• Technology area (CPC G): Physics
• CPC primary: G01R31/318516
• WIPO field: Measurement
• WIPO sector: Instruments

Abstract

A function check of a programmable logic array is performed in which input lines, product term lines and ground lines are combined into an AND plane and output lines, product term lines and ground lines are combined into an OR plane. The aim is a simple method of function check which permits any potentially-existing fault to be detected. The check is achieved by generating, with a test data generator, bit patterns and applying the same to the input lines, and, through the use of a shift register, successively sensitizing the product term lines either individually or in groups, i.e. disconnecting the same from ground potential. The bit patterns occurring at the output lines are supplied to a test data evaluator. The area of use is in logic circuitry of data processing technology.