Process for positioning an electrical contact hole between two interconnection lines of an integrated circuit
US4518629A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Dec 8, 1983 |
| Grant date | May 21, 1985 |
| Priority date | — |
| Expiry date | Dec 8, 2003 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/768
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Process for positioning an electrical contact hole between a first and a second interconnection line of an integrated circuit. The first interconnection line is produced by depositing an insulating coating on the complete integrated circuit, depositing a first material coating on said insulating coating, etching the first material coating, defining the dimensions of the electrical contact hole by masking with resin, etching the insulating coating, eliminating the mask and the remaining first material coating. The second interconnection line is produced by depositing a conductive coating on the complete integrated circuit, on which is deposited a second material coating, which is etched, so as to only leave material at the locations of the electrical contact hole, followed by the deposition of a resin coating, etching the area of the conductive coating where there is neither resin nor the residual second material coating and eliminating the latter and the resin coating.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.