Cascoded PLA array
US4518874A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 20, 1984 |
| Grant date | May 21, 1985 |
| Priority date | — |
| Expiry date | Jan 20, 2004 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/923
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A bipolar transistor integrated circuit PLA is disclosed. The array includes a first and second mutually isolated epitaxial regions in a semiconductor substrate. A plurality of common collector bipolar transistors are formed in the first epitaxial region with selected ones of the plurality having their emitters connected in common to a first current source. A second plurality of common collector bipolar transistors in the second epitaxial region have the emitters of selected ones of the second plurality connected in common to the first epitaxial region. The bases of the corresponding pairs of transistors from the first and second epitaxial region are connected to an input signal source. The second epitaxial region is connected to an output node. In this manner, a cascode connected PLA is formed which eliminates the need for surplus current sources required in the prior art. The dot OR formed by the circuit effectively merges the prior art OR array with the search array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.