Stable rail sense amplifier in CMOS memories
US4518879A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Aug 31, 1983 |
| Grant date | May 21, 1985 |
| Priority date | — |
| Expiry date | Aug 31, 2003 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/067
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A stable sense rail amplifier for CMOS memories is provided allowing very small voltage swings at or very close to the power supply rail to be transformed into substantially rail-to-rail swings. The input of the amplifier is coupled to the output of memory cells which may be designed to have output swings of 200 millivolts or less. These output swings are shifted to approximately the center of the range between the supply voltage and ground. While the level shifting is performed a small amount of linear gain is added. Subsequently the shifted signal is applied to a linear high gain amplifier stage. The high gain amplifier has as its output a substantially rail-to-rail signal. The total delay from the input rail of the amplifier to the high gain inverting amplifier stage is limited to the transfer time of a single CMOS FET. The amplifier is self-biasing and self-referencing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.