Gate-coupled field-effect transistor pair amplifier
US4518926A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Dec 20, 1982 |
| Grant date | May 21, 1985 |
| Priority date | — |
| Expiry date | Dec 20, 2002 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F3/345
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An enhancement mode (104, 204, 404) and a depletion mode (102, 202, 402) pair of N-channel MOS transistors have their drain-source conduction paths connected in series and provided with a bias current means (120, 220, 306, 410). The gates (106, 206, 308, 310) are coupled together as an input node. In one embodiment (100) their bulk regions are source-connected and the output (118) is from the source of the enhancement mode device (104) to obtain a source follower configuration amplifier. In a second embodiment (200), the output (218) is taken from the drain (208) of the depletion mode device (202) to obtain a common source configuration amplifier. Two source follower pairs (302, 304) are disclosed connected in parallel to form a differential input voltage amplifier stage (300). A common source pair (402, 404) is disclosed in combination with an additional enhancement mode transistor (406) to form a current mirror (400).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.