I/O Bus clock
US4519034A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 28, 1982 |
| Grant date | May 21, 1985 |
| Priority date | — |
| Expiry date | Sep 28, 2002 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4217
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Fully synchronous operation is provided by the use of separate frame and clock signals in each of the two directions relative to the IOCP, with all these signals controlled by the IOCP. The transmit (outbound) clock and frame signals (TCLK and TFRM) are simply sent on two lines from the IOCP to a bus terminator at the far end with the devices connecting to these lines in sequence. The receive (inbound) clock and frame signals (RCLK and RFRM) also originate at the IOCP, but their lines go directly to the far end where they are turned around and sent back to the IOCP with the devices being coupled to these lines in the reverse sequence. This provides a pair of signals that travel toward the IOCP but are still controlled by it for timing the incoming data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.