PNP comparator circuit having beta current error cancellation
US4521697A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Dec 27, 1982 |
| Grant date | Jun 4, 1985 |
| Priority date | — |
| Expiry date | Dec 27, 2002 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R17/00
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A comparator circuit comprising a pair of PNP input transistors having their collector-emitter paths coupled between first and second conductors. The output of the comparator is coupled to the base of a PNP transistor. The inputs of the comparator are coupled to the bases of the pair of PNP transistors and receive differential input signals thereat. A resistive element is connected between the input and base of one of the pair of transistors to produce an offset voltage which cancels any offset voltage produced at the input of the comparator caused by an error current that flows through the other one of the pair of transistors. The error current is due to base current flow from the PNP transistor that is connected to the output of the comparator.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.