Method of and circuit arrangement for reading an integrated semiconductor store with storage cells in MTL (I.sup.2 L) technology
US4521873A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 2, 1982 |
| Grant date | Jun 4, 1985 |
| Priority date | — |
| Expiry date | Sep 2, 2002 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/416
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of and a circuit arrangement for reading an integrated MTL(I.sup.2 L) store are described, wherein prior to or during a read operation, line capacities are discharged and in addition to the word line drivers and the bit line drivers, a read/write circuit is provided. Simultaneously with the selection of a word line (WL) or with a slight time delay (t1), two identical current sources (IRD0) are connected by means of two switches (S0 and S1) to the relevant bit lines (B0 and B1). As a result, the two injectors of the two bit line PNP transistors (T1 and T4) are supplied with the same currents. In a second phase (t2), the current sources (IRD0) are switched off so that the duration of the second time phase (t2) considerably exceeds the storage time constant (.tau.e) of the bit line PNP transistor (T4) connected to the switched "OFF" NPN transistor (T3) of a cell. The effective storage time constant (.tau.SAT) of the bit line PNP transistor (T1 ), connected to the switched on NPN cell transistor (T2), considerably exceeds the storage time constant (.tau.e). As a result of the different time constants (.tau.e and .tau.SAT), the two storage charges (Q1 and Q4) are discharged at …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.