Bus selection control in a data transmission apparatus for a multiprocessor system
US4523272A · kind A · utility
Assignees
Inventors
Key dates
| Filing date | Apr 8, 1982 |
| Grant date | Jun 11, 1985 |
| Priority date | — |
| Expiry date | Apr 8, 2002 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/374
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a multiprocessor system having a main memory and a plurality of processors connected through common address bus, data bus and answer bus for data transfer, a data transmission apparatus is provided for each of the main memory and the processors and includes bus request control lines for transferring bus request signals and bus control signals, and a bus controller for separately controlling selections of the address bus, the data bus and the answer bus in response to the signals on the bus request control lines and the request signal. Overlapped processing such as data write and data write answer or data read and data read answer in one cycle is possible.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.