Complementary FET ripple carry binary adder circuit
US4523292A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Sep 30, 1982 |
| Grant date | Jun 11, 1985 |
| Priority date | — |
| Expiry date | Sep 30, 2002 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/503
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A binary ADDER stage for producing SUM and Carry signals is constructed with five transistors, an exclusive OR gate and an exclusive NOR gate. The two digits to be added are applied to the exclusive OR gate, the output of which is connected to one input of the exclusive NOR gate and to the gate electrode of a first N-type transistor. The second input of the exclusive NOR gate is connected to a carry input terminal, and the output of the exclusive NOR provides the sum of the two digits plus the carry. The conduction path of the first N-type transistor is connected between the carry input and carry output terminals and is conditioned to conduct when the input digits differ. Second and third N-type transistors are serially connected between the carry out terminal and ground reference and have respective gate electrodes connected to the two digit input terminals respectively, for clamping the carry out terminal to a logic 0 whenever both input digits are logical 1's. Fourth and fifth P-type transistors are serially connected between the carryout terminal and positive supply potential and have respective gate electrodes connected to the two digit input terminals, respectively, for clamp…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.