Dynamic data re-programmable PLA
US4524430A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jan 11, 1983 |
| Grant date | Jun 18, 1985 |
| Priority date | — |
| Expiry date | Jan 11, 2003 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17712
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A re-programmable logic array is disclosed which has an AND array disposed for receiving n input signals on n rows of m cells per row, and an OR array providing k output lines on k rows of m cells per row. The AND and OR arrays are coupled together by m term lines. Each of the rows of the AND and OR arrays include shift register means of m charge storage elements having an input terminal coupled to the first of the m charge storage elements and an output terminal coupled to the mth one of the m charge storage elements. Multiplexors are coupled to each of the rows of both the AND and OR arrays to select between a programming operation and a recirculating refresh operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.