Transient signal suppression circuit
US4525635A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Dec 15, 1982 |
| Grant date | Jun 25, 1985 |
| Priority date | — |
| Expiry date | Dec 15, 2002 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/013
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An input signal is applied to a first flip-flop whose output is coupled to the input of a second flip-flop. The two flip-flops are clocked, at a time t.sub.1 and at a subsequent time t.sub.2, for storing the value (SI.sub.1) of the input signal at time t.sub.1 in one flip-flop and for storing the value (SI.sub.2) of the input signal at time t.sub.2, in the other flip-flop. Logic gates coupled between the first and second flip-flops and a third, set/reset, flip-flop sense the values (SI.sub.1 and SI.sub.2) of the input signal stored by the first and second flip-flops and either: (a) set the third flip-flop to a condition indicative of the value of the input signal at times t.sub.1 and t.sub.2 if SI.sub.1 is equal to SI.sub.2 ; or (b) maintain the third flip-flop undisturbed in the state to which it was set just prior to t.sub.1 if SI.sub.1 is not equal to SI.sub.2.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.