Interface arrangement for buffering communication information between a transmitting and receiving stage of a time-space-time digital switching system
US4525831A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 22, 1983 |
| Grant date | Jun 25, 1985 |
| Priority date | — |
| Expiry date | Jun 22, 2003 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04Q11/06
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
An interface arrangement is shown compensating for timing delays during transmission of communication information between a transmitting and receiving stage of a T-S-T digital switching system. The arrangement includes a buffer at the receiving stage having first and second storage files. During a first time slot communication information is written in the first file using control signals transmitted along with the communication information while simultaneously the second file is read using a local control signal. In the subsequent time slot the second file is written to and the first file is read, providing a one time slot slip between the transmitting and receiving stages.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.