High-speed memory and memory management system
US4527232A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jul 2, 1982 |
| Grant date | Jul 2, 1985 |
| Priority date | — |
| Expiry date | Jul 2, 2002 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0292
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for accessing a particular location in a main memory of a computer in which virtual addresses from a CPU are separated into direct and indirect address segments. The direct address segment is applied directly to one of row and column control lines that identify such location in the memory and the indirect address segment is translated into a real address segment and applied to the other of the row and column control lines of the main memory that identify the particular memory location. The row and column control lines are strobed with sequential pulses such that the control line to which the direct address segment is applied is strobed prior to the control line to which the translated real address segment is applied.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.