Simulator system for logic design validation
US4527249A · kind A · utility
111Cited by
5References
5Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Oct 22, 1982 |
| Grant date | Jul 2, 1985 |
| Priority date | — |
| Expiry date | Oct 22, 2002 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/33
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A hardware network or system is disclosed for testing LSI and VLSI logic device design and system design by simulation utilizing individual gate functions. The simulator system uses switching logic, random access memory, and a state table device to simulate particular test routines to test device design with functions which may appear in random or semi-random sequence.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.