Variable radix processor
US4528641A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Nov 16, 1982 |
| Grant date | Jul 9, 1985 |
| Priority date | — |
| Expiry date | Nov 16, 2002 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/49915
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A variable radix processor is constructed on 1.25 micrometer CMOS/SOS. The processor, based upon a predetermined algorithm, is constructed to process radix 2 to 7 data wherein the data is input in a parallel-by-word, parallel-by-bit format. A format selection switch has the data input whereafter a plurality of switches outputs an address format to a bit-slice multiply-adder. The bit slice multiply-adder has ROMs addressed by the format selection switch. Based upon the predetermined algorithm, each unique address format causes the ROMs to output a unique word in parallel bits to a tally cascade circuit and then to a fast-carry adder. The processor can operate on a transfer function such as Z.sub.A =.+-.(A.+-.C), Z.sub.B =B where A=.SIGMA.a.sub.i X.sub.i, B=b.sub.i X.sub.i with very high throughput rates such as 380 million operations per second.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.