Memory system with built in parity
US4528666A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 3, 1983 |
| Grant date | Jul 9, 1985 |
| Priority date | — |
| Expiry date | Jan 3, 2003 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1076
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory apparatus including an array of storage elements connected to several addressing lines for selectively connecting a group of the storage elements to multiple data lines. The memory apparatus further includes a parity circuit connected to the data lines and storage elements for selectively generating parity to designate the validity of the selected group of data connected in the portion of storage elements selected by the address lines and storing the parity in the array with the data. Control circuitry is further included for controlling the generation of parity by the parity circuit. The parity generation in this memory system is programmable according to control lines that are connected to the control circuit. The parity circuit may generate the parity output either in the same cycle as the memory access or in the next succeeding cycle of memory access. The output buffer for the parity signal may also be programmable in either a push-pull or a pull-down only configuration.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.