Central processing unit for executing instructions of variable length having end information for operand specifiers
US4530050A · kind A · utility
Assignees
Inventors
Key dates
| Filing date | Aug 17, 1982 |
| Grant date | Jul 16, 1985 |
| Priority date | — |
| Expiry date | Aug 17, 2002 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3016
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A central processing unit for executing instructions of variable length in which an operand specifier for specifying the addressing mode of an operand is independent of an operation code for ascertaining the kind of an operation and the number of operands. Each operand specifier is formed of one or more data bytes, and has a stop bit flag indicating whether or not the particular operand specifier is the last operand specifier. By adding the stop bit flag, the operand specifier can be shared, and different processing can be executed with an identical operation code. In a case where, when operation code decoding means has provided an output indicative of the last operand, the stop bit flat is not detected in the corresponding operand specifier, the corresponding instruction is detected as an error.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.