Circuit for reducing errors in a data receiver
US4530104A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jun 30, 1983 |
| Grant date | Jul 16, 1985 |
| Priority date | — |
| Expiry date | Jun 30, 2003 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2027/0069
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
In a data receiver, a complex data signal after demodulation and sampling is applied to an equalizer which provides an improved signal which is applied to a phase and amplitude correction circuit for correction utilizing a complex reference vector. The corrected signal is applied to a decision circuit the input and output of which are applied to a difference determinator circuit, the output of which is a complex residual error signal utilized in conjunction with a plurality of gain factors generated in a gain factors generator to determine the reference vector. The gain factors vary in time from transmission initialization such that optimal compensation for transmission disturbances is achieved both at initialization and after stabilization.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.