Shift register delay circuit
US4530107A · kind A · utility
11Cited by
7References
16Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Sep 16, 1982 |
| Grant date | Jul 16, 1985 |
| Priority date | — |
| Expiry date | Sep 16, 2002 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03H17/0009
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The clock signal to a fine delay shift register is divided by the number of fine delay bits for application to a coarse delay shift register such that two serially connected shift registers can provide a range of delays equivalent to a shift register having a number of bits equal to the product of the bits of the two shift registers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.