Digital span reframing circuit
US4531210A · kind A · utility
6Cited by
14References
7Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 22, 1983 |
| Grant date | Jul 23, 1985 |
| Priority date | — |
| Expiry date | Jun 22, 2003 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04Q11/04
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
In a telecommunications switching system, which has a switching network connected to a number of asynchronous digital spans, a digital span reframing circuit continuously reframes and resynchronizes each of the digital spans that are detected as lacking proper framing. The digital span reframing circuit realigns both framing and super framing, TS bits and FS bits, for proper digital span reception.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.