Electrically reprogrammable non volatile memory cell floating gate EEPROM with tunneling to substrate region
US4532535A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 16, 1982 |
| Grant date | Jul 30, 1985 |
| Priority date | — |
| Expiry date | Aug 16, 2002 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/686
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An electrically erasable and reprogrammable non volatile memory cell is disclosed which is implemented in CMOS polycrystalline silicon gate transistor technology and comprises a p-channel MOS transistor the gate of which forms a first portion of a floating electrode. A second portion of said floating electrode has a substantially larger surface than the two other portions and is placed on a field oxide layer. A third portion of the floating electrode is placed on an injection oxide layer which is thinner than the gate oxide layer of the transistor. A p.sup.- -doped well is formed under said third portion and is connected electrically to a write control electrode. An erase control electrode is arranged opposite the second portion of the floating electrode. The disclosed memory cell can be erased and reprogrammed through relatively low control voltages of a single polarity and these processes lead only to very small current consumption. The control voltages can thus be produced by means of a voltage multiplier which can be integrated on the same substrate and be controlled by a battery constituting the voltage supply source of the memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.