Real time single frame memory for converting video interlaced formats
US4532546A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 4, 1984 |
| Grant date | Jul 30, 1985 |
| Priority date | — |
| Expiry date | Jan 4, 2004 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05G1/60
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
Circuitry for converting interlaced video data to non-interlaced video data at 30 frames per second, real time video rate, where rows of successive lines of video data applied to a single frame memory are provided having data control means including readin and readout means for initially sequentially loading each row of memory with lines of interlaced video data of the first frame sequentially applied to the memory and thereafter reading out successive memory rows of the first frame from memory, while replacing each line readout by whatever line of the second frame is applied to memory in real time just after readout, until all lines of data of the second frame are inserted into memory. Successive frames are read out using a row addressing increment of N/2 for the next frame and repeating similar readin and readout of subsequent frames while multiplying the denominator of the address incrementing factor by two for each subsequent frame until the factor would be less than unity, and thereafter increasing the factor back to N/2 to repeat the cycle to process subsequent frames.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.