Parity checking arrangement for a remote switching unit network
US4532624A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Nov 3, 1983 |
| Grant date | Jul 30, 1985 |
| Priority date | — |
| Expiry date | Nov 3, 2003 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04Q11/06
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
Circuitry for validating the integrity of PCM data transmitted through a digital switching network is shown. The space stage of the switching system requires that appropriate data validity be maintained throughout. A parity scheme is employed to fulfill this requirement. For detection of invalid parity, an alarm notification is sent to the central processing unit (CPU) of the switching system. The CPU may then interrogate the space switching circuitry to determine the particular location of the parity failure. In addition, the circuitry provides for a testing feature, such that, the operation of the parity checking circuits may be validated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.