System for periodically reading all memory locations to detect errors
US4532628A · kind A · utility
41Cited by
6References
3Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Feb 28, 1983 |
| Grant date | Jul 30, 1985 |
| Priority date | — |
| Expiry date | Feb 28, 2003 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0409
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory checking circuit for periodically reading the data from all locations therein. The circuit includes logic to correct and restore data from locations where an error has occurred. The circuit quickly identifies all memory locations present during search mode at a fast rate and reads all present locations at a slower rate during normal mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.