Non-volatile memory protection circuit with microprocessor interaction
US4534018A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 29, 1983 |
| Grant date | Aug 6, 1985 |
| Priority date | — |
| Expiry date | Apr 29, 2003 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG07B2017/00403
- WIPO fieldControl
- WIPO sectorInstruments
Abstract
A method and associated apparatus for controlling the erasure and writing of data in non-volatile memory during the power up, power down and normal operating cycles of an electronic postage meter is disclosed. The apparatus monitors the input power signal and provides an enable signal when the input signal reaches a first predetermined threshold. The apparatus transmits a reset signal to inhibit the generation of a write or erase signal to a microprocessor prior to the input power signal reaching a first predetermined threshold voltage. The apparatus provides the erase signal to the non-volatile memory after the input power signal reaches the first predetermined voltage. The apparatus then applies a bias voltage to a terminal of the memory to allow for the erasure of data therefrom. A warning signal is provided to the microprocessor when the input signal falls below a specified value. The output enable signal is removed when the input signals falls below a second predetermined voltage. The apparatus transmits the write signal and applies a bias voltage to the terminal to allow for writing to the memory when the write signal and enable signal are coincident. Finally, the reset signa…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.