Plural communication channel protocol support systems
US4534023A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 7, 1983 |
| Grant date | Aug 6, 1985 |
| Priority date | — |
| Expiry date | Oct 7, 2003 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04Q11/0428
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
Protocol support and message buffering circuitry is used to transmit call status, control and terminal management information bidirectionally over associated conductor pairs as signalling messages between a system processor and a phone and/or terminal served by the system and connected to each conductor pair. This information is transmitted serially in a modified HDLC format as a one bit signalling field of a multiplexed data frame. At each transmitting end, the message information is converted from a parallel to a serial format, transmitted serially as the signalling bit of successive frames, and reconverted to parallel at the receiving end. Ports terminate the system end of the conductor pairs and are mounted four to the board. Each board contains circuitry, such as registers and the like, common to the signalling message protocol support and message buffering circuitry of all four ports. The processor scans, reads and writes these common registers via the I/O bus to determine the status of each port and to exchange messages with the remote phones and terminals served by the ports. Multiplexing is used on the signalling message so that the system processor can direct a message in…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.