Switch logic for shift register latch pair
US4535467A · kind A · utility
12Cited by
5References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 30, 1982 |
| Grant date | Aug 13, 1985 |
| Priority date | — |
| Expiry date | Nov 30, 2002 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/2885
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A Level Sensitive Scan Design (LSSD) Shift Register Latch pair implemented in current switch logic is disclosed. The arrangement is characterized by the logic used to control the L1 and L2 latches being implemented in Differential Cascode Current Switch logic and the L1/L2 latches being coupled to only one current source. A "merged" L1/L2 latch arrangement employing only one current source is provided for an LSSD testing environment.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.