Method and resulting structure for selective multiple base width transistor structures

US4535531A · kind A · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Harsaran S. Bhatia · Beacon, US
• Jack A. Dorler · Poughkeepsie, US
• Santosh P. Gaur · Wappingers Falls, US
• John S. Lechaton · Wappingers Falls, US
• Joseph M. Mosley · Hopewell Junction, US
• Gurumakonda R. Srinivasan · Poughkeepsie, US

Key dates

• Filing date: Mar 22, 1982
• Grant date: Aug 20, 1985
• Expiry date: Mar 22, 2002

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/038
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A process is described which permits the fabrication of very narrow base width bipolar transistors in selected areas of an integrated circuit chip and bipolar transistors of wider base width on other selected areas of the same integrated circuit chip. The ability to selectively vary the transistor characteristics from one region of an integrated circuit chip to another provides a degree of freedom for design of integrated circuits which is valuable. The bipolar transistors on an integrated circuit chip are processed up to the point of emitter formation using conventional techniques. But, prior to the emitter formation, the base area which is to be the emitters of the selected region having the very narrow base transistors is dry etched using reactive ion etching. The existing silicon nitride/silicon dioxide layers with the emitter opening therein are used as the etching mask for this reactive ion etching procedure. Once the etching is completed to the desired depth, the normal processing is resumed to form the emitter and rest of the metallization.