Programmable oscillator with power down feature and frequency adjustment
US4536720A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 14, 1983 |
| Grant date | Aug 20, 1985 |
| Priority date | — |
| Expiry date | Nov 14, 2003 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/70
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A programmable oscillator is provided for use on an integrated circuit chip. The oscillator includes a plurality of inverter delay stages connected in tandem between an input and an output node. A single FET device couples a node common to all of the inverter delay stages to a ground potential. Another FET device controls the input node. When a logic enabling signal is appropriately applied to the FET devices, the oscillator is controlled so that internal nodes of the oscillator float high when it is off and no energy is dissipated. In addition, the amount of delays between the delay stages and the input stage of the load is such that the load supplies the greater ratio of delays. This ensures that the oscillator's frequency of oscillation tracks the switching speed of the load.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.