Bit serial convolutional decoder for VLSI implementation
US4536878A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 20, 1982 |
| Grant date | Aug 20, 1985 |
| Priority date | — |
| Expiry date | Sep 20, 2002 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/41
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A decoder for forward-error-correcting (FEC) convolutional codes. The decoder uses the Viterbi algorithm for decoding the rate 1/2, constraint length 7 code with generator polynomials x.sup.6 +x.sup.5 +x.sup.3 +x.sup.2 +1, and x.sup.6 +x.sup.3 +x.sup.2 +x+1. The architecture of the instant decoder is appropriate for implementation on a single, monolithic VLSI integrated circuit chip and includes a branch metric calculator circuit which produces output signals representative of input symbol signals. These output signals are supplied to a metric update circuit which evaluates the signals from the calculator circuit and provides decisions to a path update circuit which converges the signals thereto and the output signals of which are evaluated by a majority vote circuit which produces data output signals representative of data input signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.