(1,8) Data encoder/decoder
US4538189A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Feb 6, 1984 |
| Grant date | Aug 27, 1985 |
| Priority date | — |
| Expiry date | Feb 6, 2004 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T9/005
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
The present invention comprises circuitry for encoding and decoding data according to a (1,8) run-length-limited, variable-length code word scheme. The encoder comprises three four-stage shift registers, two groups of logic gates and a final set of flip flops for clocking the encoding data at twice the incoming data frequency. One set of logic gates uses the outputs of each shift register to produce the encoded data, which is then reclocked at the data frequency. The other set of logic gates uses the outputs of all three sets of shift registers to locate the word boundaries, and supplies this information as input to the third shift register. The decoder consists of a twelve-stage shift register, two sets of logic gates, three single flip flops and a two-to-one multiplexer. One set of logic gates provides decoding for the odd-numbered encoded bits and the other set decodes the even numbered bits. The outputs are then reclocked by a flip flop at half the decoded data rate, and are multiplexed and reclocked at the decoded data rate. Clock circuitry for generating various clocking signals required in the operation of the encoder circuit is also shown.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.