Address translation buffer
US4538241A · kind A · utility
20Cited by
3References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 14, 1983 |
| Grant date | Aug 27, 1985 |
| Priority date | — |
| Expiry date | Jul 14, 2003 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/1027
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus is disclosed that translates virtual memory addresses into physical memory addresses. In particular, this apparatus comprises a plurality of rows of content addressable memory cells, a corresponding plurality of random access memory cells and another corresponding plurality of control circuits. The content addressable memory cells store the virtual memory addresses and the random access memory cells store the physical memory addresses. The control circuits are coupled to both the content addressable and the random access memory cells and are disposed for controlling the operation of the apparatus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.